1. Field of the Invention
Embodiments of the invention relate generally to information processing systems. More specifically, embodiments of the invention provide an improved system and method for managing memory requests that are coordinated between a system memory controller and a graphics memory controller.
2. Description of the Related Art
The computing power of single instruction, multiple-data (SIMD) pipelines and the enhanced programmability of unified shaders supported by recent graphics processing units (GPUs) make them increasingly attractive for scalable, general purpose programming. Currently, there are numerous academic and industrial efforts for developing general purpose GPUs (GPGPUs), including the Advanced Micro Devices (AMD) Fusion®. Some GPGPU designs, including the Fusion®, incorporate x86 central processing units (CPUs) to provide advanced graphics engines with an efficient GPGPU hardware substrate.
While there are many possible approaches to integrating CPUs and GPUs, one solution is to have them communicate through each other's memory systems. For example, a CPU would have a communication path to the system memory managed by a CPU memory controller, and a GPU would have a communication path to the graphics memory managed by a GPU memory controller, just as if they were independent systems. To support communications between the CPU and GPU, the GPU would have an additional path to the system memory and the CPU would have an additional path to the graphics memory.
These additional paths support memory requests that cross the CPU/GPU boundary. In various implementations, the paths may be dedicated wires for low access latencies or conventional paths through an I/O bus (e.g., PCIe), where the system memory is accessed with direct memory access (DMA) by the GPU, and the graphics memory is accessed with memory-mapped I/O by the CPU. Ideally, individual memory requests sent through these additional paths are processed efficiently by the memory controllers. However, simply providing these additional memory paths generally fails to address typical performance and functionality issues caused by the differences between the CPU and GPU memory controllers.